Recessed channel
US6963108B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2003 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Oct 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
Abstract
A memory cell with reduced short channel effects is described. A trench region is formed in a semiconductor substrate. A source region and a drain region are formed on opposing sides of the trench region, wherein a bottom of the source region and a bottom of the drain region are above a floor of the trench region. A gate dielectric layer is formed in the trench region of the semiconductor substrate between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A control gate is formed on the semiconductor substrate above the recessed channel region, wherein the control gate is separated from the recessed channel region by the gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.