Inkuk Kang
23Patents
6h-index
41Co-inventors
69Inventor score
Filing activity: Dec 3, 2002 → Jun 26, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7033957B1 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Emerging Cross-Sectional Technologies | 42 | Expired |
| US6803275B1 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Electricity | 24 | Expired |
| US6963108B1 | Recessed channel | Electricity | 19 | Expired |
| US6969886B1 | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | Electricity | 18 | Expired |
| US9853039B1 | Split-gate flash cell formed on recessed substrate | Electricity | 11 | Active |
| US6974989B1 | Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing | Electricity | 6 | Expired |
| US7060564B1 | Memory device and method of simultaneous fabrication of core and periphery of same | Electricity | 4 | Expired |
| US7288487B1 | Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure | Electricity | 4 | Expired |
| US7242102B2 | Bond pad structure for copper metallization having increased reliability and method for fabricating same | Electricity | 3 | Expired |
| US10872898B2 | Embedded non-volatile memory device and fabrication method of the same | Electricity | 3 | Active |
| US8987092B2 | Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges | Electricity | 2 | Active |
| US8551858B2 | Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory | Electricity | 2 | Active |
| US8026169B2 | Cu annealing for improved data retention in flash memory devices | Electricity | 2 | Active |
| US12029041B2 | Method of forming high-voltage transistor with thin gate poly | Electricity | 1 | Active |
| US7122465B1 | Method for achieving increased control over interconnect line thickness across a wafer and between wafers | Electricity | 1 | Expired |
| US8487373B2 | SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same | Electricity | 1 | Active |
| US10242996B2 | Method of forming high-voltage transistor with thin gate poly | Electricity | 1 | Active |
| US8076199B2 | Method and device employing polysilicon scaling | Electricity | 1 | Active |
| US9818755B1 | Split-gate flash cell formed on recessed substrate | General | 0 | Revoked |
| US8637918B2 | Method and device employing polysilicon scaling | Electricity | 0 | Active |
| US10497710B2 | Split-gate flash cell formed on recessed substrate | Electricity | 0 | Active |
| US8742496B2 | Sonos memory cells having non-uniform tunnel oxide and methods for fabricating same | Electricity | 0 | Active |
| US11690227B2 | Method of forming high-voltage transistor with thin gate poly | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.