Method and apparatus for fast automated failure classification for semiconductor wafers
US6963813B1 · kind B1 · utility
7Cited by
23References
15Claims
0Family size
Inventors
Key dates
| Filing date | Sep 13, 2000 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Sep 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for classifying patterns of failcodes on a semiconductor wafer, in accordance with the present invention, includes determining failcodes for chips on the wafer and checking adjacent chips for each chip on the wafer having a failcode to determine a failcode pattern having a defined number of chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.