Joerg Wohlfahrt
18Patents
7h-index
21Co-inventors
55Inventor score
Filing activity: Jan 11, 2000 → Dec 30, 2003
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7187602B2 | Reducing memory failures in integrated circuits | Physics | 10 | Expired |
| US6717431B2 | Method for semiconductor yield loss calculation | Electricity | 9 | Expired |
| US6999887B2 | Memory cell signal window testing apparatus | Physics | 8 | Expired |
| US6482716B1 | Uniform recess depth of recessed resist layers in trench structure | Electricity | 7 | Expired |
| US6639824B1 | Memory architecture | Physics | 7 | Expired |
| US6553521B1 | Method for efficient analysis semiconductor failures | Physics | 7 | Expired |
| US6963813B1 | Method and apparatus for fast automated failure classification for semiconductor wafers | Electricity | 7 | Expired |
| US6800890B1 | Memory architecture with series grouped by cells | Electricity | 6 | Expired |
| US6826099B2 | 2T2C signal margin test mode using a defined charge and discharge of BL and /BL | Physics | 6 | Expired |
| US6720598B1 | Series memory architecture | Electricity | 4 | Expired |
| US6731529B2 | Variable capacitances for memory cells within a cell group | Electricity | 3 | Expired |
| US6731554B1 | 2T2C signal margin test mode using resistive element | Physics | 3 | Expired |
| US6707699B1 | Historical information storage for integrated circuits | Physics | 2 | Expired |
| US6885597B2 | Sensing test circuit | Physics | 2 | Expired |
| US6807084B1 | FeRAM memory device | Physics | 1 | Expired |
| US6856560B2 | Redundancy in series grouped memory architecture | Physics | 1 | Expired |
| US6903959B2 | Sensing of memory integrated circuits | Physics | 1 | Expired |
| US7003432B2 | Method of and system for analyzing cells of a memory device | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.