SOI trench capacitor cell incorporating a low-leakage floating body array transistor

US6964897B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Karen Bard · Hopewell Junction, US
• David M. Dobuzinsky · New Windsor, US
• Herbert L. Ho · New Windsor, US
• Mahendar Kumar · Fishkill, US
• Denise Pendleton · Wappingers Falls, US
• Michael D. Steigerwalt · Newburgh, US
• Brian L. Walsh · New Paltz, US

Key dates

• Filing date: Jun 9, 2003
• Grant date: Nov 15, 2005
• Expiry date: Jul 16, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.