Method of etching a lateral trench under an extrinsic base and improved bipolar transistor
US6964907B1 · kind B1 · utility
22Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2003 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Nov 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a <110> direction of a <100> orientation wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.