Delay system for generating control signals in ferroelectric memory devices
US6965520B1 · kind B1 · utility
9Cited by
11References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2004 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Ferroelectric memory devices and control circuits therefor are presented, in which memory array control and timing signals are derived according to tap outputs from a group of series connected delay elements. Some or all of the individual delay elements comprise one or more trim inputs and a variable delay circuit that provides an output signal a variable delay time after the delay element input signal, where the variable delay is set according to the trim inputs, allowing the control signals to be adjusted or trimmed to accommodate fabrication process variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.