CMOS tapered gate and synthesis method
US6966046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2001 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Aug 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.