Semiconductor fabrication process with asymmetrical conductive spacers
US6967143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.