Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness
US6967160B1 · kind B1 · utility
14Cited by
14References
14Claims
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Key dates
| Filing date | Jan 26, 2005 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Jan 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.