Method and apparatus for output data synchronization with system clock in DDR
US6968026B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Feb 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for substantially reducing or eliminating the timing skew caused by delay elements in a delay locked loop. A method and apparatus is disclosed wherein a rising edge of a local timing signal is established and phase-locked to a rising edge of a system clock signal by delaying the system clock signal. A falling edge of the local timing signal is established and phase-locked to a falling edge of the system clock signal by further delaying only a portion of a signal representative of the delayed clock signal. By separately delaying different portions of the system clock signal and using the separately delayed portions to establish a local timing signal, a local timing signal may be established which is compensated for the varied effects of delay elements in a delay locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.