Method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system
US6968417B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2002 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Jun 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer coupled to a control unit. The buffer may be configured to receive data on a first bus and the control unit may be configured to generate a first command type in response to receiving a first quantity of data having invalid bytes within the buffer. The control unit may be further configured to generate a second command type in response to a receiving within the buffer a second quantity of data having no invalid bytes. Further, in response to receiving a particular transaction type, the control unit may be configured to generate the second command type before the first quantity of data is received within the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.