Multithreaded processor with efficient processing for convergence device applications
US6968445B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2002 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Jan 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multithreaded processor includes an instruction decoder for decoding retrieved instructions to determine an instruction type for each of the retrieved instructions, an integer unit coupled to the instruction decoder for processing integer type instructions, and a vector unit coupled to the instruction decoder for processing vector type instructions. A reduction unit is preferably associated with the vector unit and receives parallel data elements processed in the vector unit. The reduction unit generates a serial output from the parallel data elements. The processor may be configured to execute at least control code, digital signal processor (DSP) code, Java code and network processing code, and is therefore well-suited for use in a convergence device. The processor is preferably configured to utilize token triggered threading in conjunction with instruction pipelining.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.