Backthinned CMOS sensor with low fixed pattern noise
US6969839B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2003 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Aug 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
This invention deals with the reduction in fixed pattern noise in backthinned CMOS imagers primarily for use in a vacuum environment. Reduction is achieved by effectively shielding the imager. This is done by depositing a conductive layer on the front surface prior to the attachment of a support member or by incorporating a conductive layer into the die at least extensive with the analog circuitry. This also may be achieved by leaving a void adjacent to the analog circuitry area. This void, filled with air or a vacuum specifies a low dielectric layer over critical analog circuitry. Finally there is extended across the die an adhesive or underfill material after which a support member is placed onto the underfill to provide structure to the die. The underfill and the support layer should have thermal coefficients of expansion that substantially match that of the silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.