LVTSCR ESD protection clamp with dynamically controlled blocking junction

US6970335B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Vladislav Vashchenko · Palo Alto, US
• Ann Concannon · San Jose, US
• Peter J. Hopper · San Jose, US
• Marcel ter Beek · Pleasanton, US

Key dates

• Filing date: Jul 23, 2003
• Grant date: Nov 29, 2005
• Expiry date: Dec 1, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/713

Abstract

In an SCR-based ESD protection clamp, the voltage overshoot during an ESD event is reduced by separately controlling the voltage pulse to the drain and emitter contacts of the SCR. The voltage pulse to the drain is preferably delayed using a delay circuit such as an RC circuit. This allows double conductivity modulation to be achieved with lower voltage overshoot.