Method and apparatus for improving stability of a 6T CMOS SRAM cell
US6970373B2 · kind B2 · utility
59Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2003 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Jan 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.