Charge-trapping memory cell array and method for production

US6972226B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Joachim Deppe · Dresden, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Mar 31, 2004
• Grant date: Dec 6, 2005
• Expiry date: Apr 3, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/30

Abstract

In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material of shallow trench isolations running across the wordlines.