Method for fabricating semiconductor device with improved tolerance to wet cleaning process
US6972262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2004 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Jun 12, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for fabricating a semiconductor device with an improved tolerance to a wet cleaning process. For a contact formation such as a gate structure, a bit line or a metal wire, a spin on glass (SOG) layer employed as an inter-layer insulation layer becomes tolerant to the wet cleaning process by allowing even a bottom part of the SOG layer to be densified during a curing process. The SOG layer is subjected to the curing process after a maximum densification thickness of the SOG layer is obtained through a partial removal of the initially formed SOG layer or through a multiple SOG layer each with the maximum densification thickness. After the SOG layer is cured, a self-aligned contact etching process is performed by using a photoresist pattern singly or together with a hard mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.