Integrated circuit and method for its manufacture
US6972478B1 · kind B1 · utility
575Cited by
1References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2005 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Mar 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of <100> crystalline orientation and a second region of <110> crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of <110> crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of <100> crystalline orientation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.