Isolation structures for imposing stress patterns
US6974981B2 · kind B2 · utility
105Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2002 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Feb 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.