Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6975016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2002 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Mar 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.