Circuit structure and semiconductor integrated circuit
US6975489B2 · kind B2 · utility
6Cited by
0References
30Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jan 23, 2003 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Aug 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bypass capacitor having a given capacitance is arranged on the power/ground line adjacently to a driver circuit in a chip to reduce an effect of transient phenomenon at switching. The capacitance of the bypass capacitor is preset so as to be larger than a parasitic capacitance of the driver circuit to prevent the characteristic impedance of the power/ground line from being higher than the characteristic impedance of internal wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.