Memory block erasing in a flash memory device
US6975538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2003 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Feb 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase pulse is applied to the memory block to be erased. An erase verification operation is performed to verify that each memory cell of the memory block is erased. If a memory cell has a current less than a first sense amplifier current reference level, additional erase pulses are applied to that cell until either the erase current is in the range of 30–40 μA or a maximum quantity of erase pulses have been applied. A leakage check is performed to determine if any cells have been overerased. If a cell has an erase current greater than or equal to a second sense amplifier current reference level, soft programming pulses are applied to the cell until either its erase current is less than the second reference level or a maximum quantity of soft program pulses have been applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.