Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
US6975556B2 · kind B2 · utility
2Cited by
4References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2003 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Apr 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.