Method and apparatus for fault simulation of semiconductor integrated circuit
US6975978B1 · kind B1 · utility
29Cited by
17References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 27, 2000 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Oct 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test pattern sequence is generated (101), then a logic simulation of the operation of an IC under test in the case of applying each test pattern of the test pattern sequence, and a logic signal value sequence occurring in each signal line of the IC under test (102). The logic signal value sequence in each signal line is used to register in a fault list parts (a logic gate, signal line or signal propagation path) in which a fault (a delay fault or an open fault) detectable by a transient power supply current testing using the test pattern sequence is likely to occur (103).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.