Method of forming narrow trenches in semiconductor substrates
US6977203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Nov 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3086
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.