Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it

US6977405B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Jorn Lutzen · Dresden, DE
• Bernd Goebel · Dresden, DE
• Dirk Schumann · Lübbenau/Spreewald - Lubnjow/Błota, DE
• Martin Gutsche · Dorfen, DE
• Harald Seidl · Brandenburg an der Havel, DE
• Martin Popp · Dresden, DE
• Alfred Kersch · Putzbrunn, DE
• Werner Steinhogl · Birkenfeld, DE

Key dates

• Filing date: Mar 5, 2004
• Grant date: Dec 20, 2005
• Expiry date: Mar 5, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/0385

Abstract

In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.