Thick metal layer integrated process flow to improve power delivery and mechanical buffering

US6977435B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sarah Kim · Portland, US
• Bob Martell · Portland, US
• Dave Ayers · Fremont, US
• R. Scott List · Beaverton, US
• Peter K. Moon · Portland, US
• Steven Towle · Phoenix, US

Key dates

• Filing date: Sep 9, 2003
• Grant date: Dec 20, 2005
• Expiry date: Sep 9, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.