Semiconductor device
US6977858B2 · kind B2 · utility
9Cited by
3References
9Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Apr 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises, a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.