Method for exposing at least one or at least two semiconductor wafers

US6979522B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Heiko Hommen · Dresden, DE
• Ralf Otto · Wiesbaden, DE
• Thorsten Schedel · Dresden, DE
• Sebastian Schmidt · Weisendorf, DE
• Thomas Fischer · Umkirch, DE

Key dates

• Filing date: Aug 6, 2003
• Grant date: Dec 27, 2005
• Expiry date: Aug 6, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F9/7046
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A batch of semiconductor wafers are exposed after an alignment in a wafer stepper or scanner and each of their alignment parameters are determined. Using, e.g., a linear formula with tool specific coefficients, the overlay accuracy can be calculated from these alignment parameters in advance with a high degree of accuracy as if a measurement with an overlay inspection tool had been performed. The exposure tool-offset can be adjusted on a wafer-to-wafer basis to correct for the derived overlay inaccuracy. Moreover, the alignment parameters for a specific wafer can be used to change the tool-offset for the same wafer prior to exposure. The required inspection tool capacity is advantageously reduced, the wafer rework decreases, and time is saved to perform the exposure step.