Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs
US6979526B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Nov 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of manufacturing a resistive semiconductor memory device (10), comprising depositing an insulating layer (34) over a workpiece (30), and defining a pattern for a plurality of alignment marks (22) and a plurality of conductive lines (54) within the insulating layer (34). A resist (50) is formed over the alignment marks (22), and a conductive material (52) is deposited over the wafer to fill the conductive pattern. The wafer is chemically-mechanically polished to remove excess conductive material from over the insulating layer and form conductive lines (54). The resist (50) is removed from over the alignment marks (22), and the alignment marks (22) are used for alignment of subsequently deposited layers of the resistive memory device (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.