Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process
US6979869B2 · kind B2 · utility
36Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2003 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Jan 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/815
Abstract
A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.