Method and circuit for normalization of floating point significants in a SIMD array MPP
US6981012B2 · kind B2 · utility
3Cited by
7References
39Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2001 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Feb 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significand alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.