Memory and method for employing a checksum for addresses of replaced storage elements
US6981175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Jun 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each having a plurality of fusible links and being operable to store a replacement address, each replacement address identifying one of the storage elements of the memory array to be replaced by an associated one of the replacement storage elements and forming a respective 2m bit row or 2n bit column of a fuse array; a vector generator operable to produce a 2n bit row vector based on the rows of the fuse array and to produce a 2m bit column vector based on the columns of the fuse array; and a compression unit operable to produce a row checksum from the row vector and to produce a column checksum from the column vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.