Methods for filling high aspect ratio trenches in semiconductor layers
US6982207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2003 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Sep 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The gas flow and RF bias are then selected to provide a low etch to deposition ratio while the trenches are completely filled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not bemused to interpret or limit the scope or meaning of the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.