Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
US6982210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2003 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Feb 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a multilayer semiconductor structure that includes an irregular layer. In an embodiment, the method includes providing a layer of irregular material on a donor substrate. The irregular layer has a flat face at an interface with the donor substrate, and has an opposite, irregular face. Next; a weakened zone is created at a predetermined depth within the donor substrate. An intermediate layer of material is then provided that covers the irregular face of the irregular layer, the intermediate layer providing a substantially flat surface. The substantially flat surface of the intermediate layer is then bonded to a receiver substrate, and the donor substrate is detached along the weakened zone to form the multilayer semiconductor structure. The multilayer structure includes an useful layer, the irregular layer, the intermediate layer and the receiver substrate, wherein all of the irregular material of the irregular layer is present in the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.