Gate-induced strain for MOS performance improvement
US6982433B2 · kind B2 · utility
43Cited by
10References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2003 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Aug 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed an apparatus including a substrate defining an interior of the apparatus, a device exterior to the substrate including a gate electrode, and a straining layer exterior to the gate electrode and exterior to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.