MRAM architecture with a bit line located underneath the magnetic tunneling junction device
US6982445B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2003 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Oct 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method and system for providing and using a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells, at least a first write line, and at least a second write line. Each of the magnetic memory cells includes a magnetic element having a top and a bottom. The first write line(s) are connected to the bottom of magnetic element of the first portion of the plurality of magnetic memory cells. The second write line(s) reside above the top of the magnetic element of each of a second portion of the magnetic memory cells. The second write line(s) are electrically insulated from the magnetic element of each of the second portion of the plurality of magnetic memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.