Random pattern weight control by pseudo random bit pattern generator initialization
US6983407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2003 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Dec 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/84
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A plurality of pseudo random bit-pattern generators (PRPGs), advantageously linear feedback shift registers (LFSRs), having predetermined lengths and individual different tap locations for providing a respective sequence of pseudorandom bit-patterns. An output from a predetermined respective tap location at each LFSR is fed to a common OR-gate, a selected subset of the LFSRs are initialized with all bit storing locations to “0” in order to generate a respective permanent “0”-bit sequence, and the output of the OR-gate is used for reading the weighted or flat random bit output-pattern thereof. By controlling the number of zero-set LFSRs—a subset of the LFSRs—the weight of the generated output-pattern can be controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.