Semiconductor memory device with static memory cells
US6984859B2 · kind B2 · utility
6Cited by
6References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 17, 2004 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | May 28, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An access transistor, provided between a storage node in a memory cell and a bit line is formed of a P channel MOS transistor including P type first and second impurity regions formed in an N type well and a gate electrode. Buried interconnection is formed of metal having high melting point such as tungsten and provided stacked on a driver transistor formed on a main surface of a P type well and the access transistor. A polysilicon film forming a P channel TFT as a load element is formed on the buried interconnection, which is planarized, with an interlayer insulating film interposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.