Overlay marks, methods of overlay mark design and methods of overlay measurements
US6985618B2 · kind B2 · utility
63Cited by
70References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2002 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Oct 18, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing an overlay mark, which is used to determine the relative position between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate, is disclosed. The method includes optimizing the geometry of a first element of the mark according to a first scale. The method further includes optimizing the geometry of a second element of the mark according to a second scale. The method additionally includes optimizing the geometry of a third element of the mark according to a third scale.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.