Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests
US6985999B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2002 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Jan 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/306
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor prioritizes cache line fill requests according to request type rather than issuing the requests in program order. In one embodiment, the request types include blocking accesses at highest priority, non-blocking page table walk accesses at medium priority, and non-blocking store allocation and prefetch accesses at lowest priority. The microprocessor takes advantage of the fact that the core logic clock frequency is a multiple of the processor bus clock frequency, typically by an order of magnitude. The microprocessor accumulates the various requests generated by the core logic each core clock cycle during a bus clock cycle. The microprocessor waits until the last core clock cycle before the next bus clock cycle to prioritize the accumulated requests and issues the highest priority request on the processor bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.