Trench MOSFET with increased channel density
US6987040B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2004 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Sep 27, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface (56). Source regions (66, 68) are formed along a vertical wall (84) inside of the trench (60). The source regions (66, 68) have a horizontal component along the major surface (56) and a vertical component extending the vertical wall (84). The majority of the source regions (66, 68) are formed along the vertical wall (84) within the trench (60). A typical aspect ratio of the vertical length of the source regions (66, 68) to the horizontal width is greater than 3:1. An Inter-layer dielectric (ILD) layer (74) is formed on the gate structure (62) within the trench (60) below the major surface (56). A metal electrode layer (82) is formed above the major surface (56) where a portion is formed inside the trench (60) making source contact to the source regions (66, 68) inside the trench (60) along the vertical wall (84) of the trench (60).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.