Method of making cavities in a semiconductor wafer
US6987051B2 · kind B2 · utility
6Cited by
12References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2003 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Dec 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a method of making a semiconductor structure that includes a surface layer of silicon, a buried insulating layer, and a substrate. The method includes implanting atoms through at least a portion of the insulating layer; and etching the insulating layer in at least a portion of the layer through which atoms have been implanted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.