Method of improving erase voltage distribution for a flash memory array having dummy wordlines
US6987696B1 · kind B1 · utility
26Cited by
19References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2004 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Jul 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage to the dummy wordlines. In one arrangement, an electrical connection is established between the dummy wordline and the end one of the operative wordlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.