Copper damascene with low-k capping layer and improved electromigration reliability

US6989601B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Minh Van Ngo · Union City, US
• Jeremy I. Martin · Austin, US
• Hartmut Ruelke · Dresden, DE

Key dates

• Filing date: Sep 22, 2004
• Grant date: Jan 24, 2006
• Expiry date: Sep 22, 2024

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/931
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 Å to about 800 Å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.