Method and apparatus for multithreaded cache with cache eviction based on thread identifier
US6990557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2002 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Jan 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has multiple entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of a thread identifier of the given thread cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.