Semiconductor memory with vertical charge-trapping memory cells and fabrication

US6992348B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Christoph Kleint · Dresden, DE
• Joachim Deppe · Dresden, DE
• Christoph Ludwig · Radeberg, DE
• Jens-Uwe Sachse · Dresden, DE

Key dates

• Filing date: Dec 19, 2003
• Grant date: Jan 31, 2006
• Expiry date: Apr 4, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0413

Abstract

Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.