Barrier for interconnect and method
US6992389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2004 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Aug 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/04953
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.