Dual-damascene interconnects without an etch stop layer by alternating ILDs
US6992391B2 · kind B2 · utility
6Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Dec 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.